CD74HC109E
Description
The ’CD74HC109E and ’HCT109 are dual J-K flip-flops with set and
reset. The flip-flop changes state with the positive transition
of Clock (1CP and 2CP).
The flip-flop is set and reset by active-low S and R,
respectively. A low on both the set and reset inputs
simultaneously will force both Q and Q outputs high.
However, both set and reset going high simultaneously
results in an unpredictable output condition.
Features
_ Asynchronous Set and Reset
_ Schmitt Trigger Clock Inputs
_ Typical MAX = 54MHz at VCC = 5V, CL = 15pF,
TA = 25oC
_ Fanout (Over Temperature Range)
_ Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
_ Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
_ Wide Operating Temperature Range . . . -55oC to 125oC
_ Balanced Propagation Delay and Transition Times
_ Significant Power Reduction Compared to LSTTL
Logic ICs
_ HC Types
– 2V to 6V Operation
– High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
_ HCT Types
– 4.5V to 5.5V Operation CD74HC109E
– Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
-CD74HC109E CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
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